The present invention relates to simulation devices and simulation programs associated with the manufacturing of semiconductor devices, and more particularly, a simulation device and program which can be suitably used for a manufacturing process including a plurality of processing steps.
A lithography process is known as one of general semiconductor manufacturing techniques. The lithography process involves optically transferring a predetermined mask pattern to a wafer using an exposure device. The shape of the pattern (mask pattern) formed over the wafer using a predetermined photomask (hereinafter referred to as a simply “mask”) through the lithography process in this way is estimated using a lithography simulation (hereinafter referred to as a simply “simulation”) taking into consideration optical properties. The use of such simulation can also verify various types of lithography.
Related art techniques relating to the above lithography simulation are as follows.
Japanese Unexamined Patent Publication No. 2009-192811 (Patent Document 1) discloses a lithography simulation method that can achieve the estimation of a pattern with high accuracy, while suppressing increase in amount of calculation.
Japanese Unexamined Patent Publication No. 11-186152 (Patent Document 2) discloses an exposure simulation method which can calculate exposure simulation at high speed in a lithography step performed by a semiconductor manufacturing device.
Japanese Unexamined Patent Publication No. 2009-094109 discloses a calculation method for calculating a light intensity distribution (partial coherent imaging calculation) formed on the wafer surface in a short time.